Embodiments of the present invention relate generally to the fabrication of semiconductor devices, and more particularly to the fabrication of metal-insulator-metal capacitors (MIM capacitors).
Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
Capacitors are elements that are used extensively in semiconductor devices for storing an electrical charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the insulator between the plates, as examples. Capacitors are used in filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor devices.
One type of capacitor is a metal-insulator-metal capacitor (MIM capacitor), which is used often in mixed signal devices and logic devices, for example. MIM capacitors are used to store a charge in a variety of semiconductors. MIM capacitors typically require a much lower capacitance than deep trench memory capacitors, for example. A MIM capacitor may have a capacitance requirement of 1 fF/micrometer2, for example. A MIM capacitor is typically formed horizontally on a semiconductor wafer, with two metal plates sandwiching a dielectric parallel to the wafer surface. At least one of the metal plates is usually formed in a metallization layer (metal interconnect layer) of the device. MIM capacitors embedded in the back-end-of-line (BEOL) structures have been used in many very large scale integrated logic (VLSI) devices in the past.
Horizontal MIM capacitors are manufactured in the BEOL, a stage in semiconductor device fabrication that usually begins with the formation of the first metallization layer on the wafer. MIM capacitors are typically formed in the BEOL by forming a bottom capacitive plate in a first or subsequently deposited horizontal metallization layer of a semiconductor wafer using a first lithography mask. A first etch step such as a reactive ion etch (RIE) is used to transfer the mask pattern to the bottom plate. A capacitor dielectric is deposited over the bottom capacitive plate, and a second mask and RIE step is used to pattern the capacitor dielectric. A top capacitive plate material is deposited over the capacitor dielectric, and a third mask and RIE step is used to form the top capacitive plate. Each mask and RIE step adds labor and cost to the MIM capacitor fabrication process.
Alignment techniques are implemented during manufacturing processes to ensure correct alignment of the various layers with one another within semiconductor devices such as MIM capacitors. Typically, alignment marks are utilized in the layers to assist in the alignment of features in different layers.
Because metal layers are not transparent to light, lithography of a MIM capacitor metal plate layer requires topographic features for alignment and overlay measurement marks. Typically this underlying MIM capacitor layer requires a chemical mechanical polish (CMP) process as a finish step.
Alignment marks are usually formed using additional lithography and reactive ion etch (RIE) steps to generate marks on the CMP-finished surface that exposes the copper and dielectric patterns. However, forming alignment marks in this manner requires an additional RIE process step and subsequent cleaning steps, thus increasing the processing costs and also increasing the chance of leaving particles on the CMP finished level. Also, an additional lithography mask is required to pattern the alignment marks, and the additional lithography mask must be aligned to an underlying layer, which reduces the overall overlay tolerance.
Embodiments of the present invention achieve technical advantages as a method of forming MIM capacitor structures in which previous level alignment and overlay marks are preserved during the formation of the MIM capacitors, without requiring an additional reactive-ion etch (RIE) process to form alignment marks for the MIM capacitor level and subsequent layers.
In accordance with a preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a semiconductor workpiece, forming an insulating layer over the workpiece, and defining a pattern for at least one alignment mark within the insulating layer, the alignment mark pattern comprising an alignment mark. The method includes defining a pattern for a plurality of conductive lines within the insulating layer, defining a pattern for at least one metal-insulator-metal (MIM) capacitor within the insulating layer, and forming a resist over the alignment mark and MIM capacitor pattern. A first conductive material is deposited over the insulating layer to fill the conductive line pattern and form conductive lines, leaving excess first conductive material disposed over the conductive lines. The resist is removed from over the alignment mark pattern and MIM capacitor pattern and the excess first conductive material is removed from over the conductive line pattern, wherein the alignment mark pattern may be used for alignment of subsequently formed layers of the semiconductor device.
In accordance with another preferred embodiment of the present invention, a method of manufacturing a semiconductor device, includes providing a semiconductor workpiece, forming an insulating layer over the workpiece, and defining a pattern for a plurality of conductive lines within the insulating layer, the conductive line pattern comprising a first depth. The method includes defining a pattern for at least one alignment mark within the insulating layer, the alignment mark pattern comprising an alignment mark, the alignment mark comprising a second depth, defining a pattern for at least one metal-insulator-metal (MIM) capacitor within the insulating layer, the MIM capacitor pattern having a third depth, and depositing a liner over the alignment mark and conductive line pattern. The method also includes forming a resist over the alignment mark and MIM capacitor pattern, depositing a first conductive material over the insulating layer to fill the conductive line pattern and form conductive lines, leaving excess first conductive material disposed over the insulating layer, and using a chemical-mechanical process to removing the resist from over the alignment mark pattern and MIM capacitor pattern and remove the excess first conductive material and liner from over the insulating layer. MIM capacitor material layers are deposited over the insulating layer, and a chemical-mechanical process is used to remove the MIM capacitor material layers from over the insulating layer and form a MIM capacitor within the MIM capacitor pattern, wherein a topography of the alignment mark pattern is visible from the top surface of the workpiece.
Advantages of embodiments of the invention include forming a semiconductor device including MIM capacitors, wherein the same alignment and overlay measurement marks in a CMP-finished level (such as the process flow for forming conductive lines, to be described further herein) are used as the alignment and overlay measurement marks that are used to align a subsequent layer. Because the original alignment marks are preserved during the MIM capacitor formation, an additional patterning, etch and cleaning step is avoided. Furthermore, alignment is more accurate, because there is no need to align new alignment marks with already existing alignment marks. Overlay budget is increased, because an additional overlay is not required.
Other advantages include a resist being used to block conductive material deposition within the alignment marks and MIM capacitor region, beneficial in that the resist may be left intact during the conductive material CMP process, preventing the CMP slurry from entering and becoming trapped within the alignment marks and MIM capacitor patterns, thus preserving the alignment mark and MIM capacitor pattern shape.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.